# Logic Families and its Features| TTL Vs CMOS

Hello everyone, hope you all are doing great in your fields. The topic for today’s discussion is Features of Digital Logic families and subsequently, about the TTL and CMOS Logic family. Here we are also going to have a sort of comparison between CMOS and TTL. So before starting with the main topic let’s be clear with what a digital logic family or circuit is?

## What is a Digital Logic Family?

A logic family is a group of well-matched IC’s with likewise logic levels and supply voltage for performing various logic functions which have been made by using a specific circuit layout.

## Bipolar Logic Family

Certainly, the most important elements of bipolar IC are resistors, transistors, and diodes. these IC’s further consist of two types;

• Saturated IC’s (for example RTL, TTL, DCTL, DTL)
• Non-Saturated IC’s (for example ECL)

## Unipolar logic family

MOS devices are unipolar IC’s and above all, it is the only part of these circuits. the members of the MOS family are;

• PMOS
• NMOS
• CMOS (5-V and low-Voltage CMOS)

## Features of IC’s

#### 1. Speed of Operation

Moreover, the speed of a digital circuit is given in terms of propagation delay. So the input and the output waveform is;

Meanwhile, Time delay is given in terms of 50% voltage level of input and 50% voltage level of output voltage. However, there are two-time delays;

• Tphl, that is to say when output goes from high to low.
• Tplh, that is to say when output goes from low to high.

the average of these two delays subsequently, gives the net time delay of the system.

#### 2. Power Dissipation

This is the amount of power given to the IC. However, the current Icc that is drawn from the Vcc is given by,

= Vcc * Icc

= I2cc * R

In the same vein as that of time delay, it is also the average of Icc (0) and Icc (1). However, the unit of this power is Milliwatts. in other words it is known as static power dissipation. ( note:- i.e. power absorb by the system when no input is changing )

#### 3. Figure of merit

It is the speed power factor. Meanwhile, the speed is given in terms of propagation delay (N sec) and power in (mW)

Figure of merit = delay * power

generally, the figure of merit is in terms of Pico joule. Mostly the low value of the speed power factor is acceptable. time delay and power are inversely proportional to each other.

#### 4. Fan Out

This is the number of likewise gates which can be driven by a gate. High fan-out is an advantage because it reduces the need for additional hardware.

for example, the fan out of TTL is most certainly up to 10.

#### 5. Fan In

It is the number of inputs that a logic gate can manage.

for example, most of the logic gates have 1 or 2 fan in’s.

#### 6. Current and Voltage Parameters

However, the following current and voltage parameters are most used while designing a digital circuit.

Firstly let’s have all the voltage parameters;

• High-level input voltage, VIH. This is the min voltage that a gate identify as 1.
• Low-level input voltage, VIL. This is the max voltage that a gate identify as 1.
• High-level output voltage, VOH. This is the min voltage available at output with respect to logic 1.
• Similarly, Low-level output voltage, VOL.This the max voltage available at the output with respect to 0 logic level.

besides here are all the current parameters;

• Low-level input current, IIL. This is the min current which is to be given by the source corresponding to 0 level voltage.
• High-level output current, IOH. This is the max current which the gate can sink in level 1
• Low-level input current, IIL. This is the min current which is to be given by the source corresponding to 0 level voltage.
• High-level output current, IOH. This is the max current which the gate can sink in level 1.
• High-level output current, ICC (1) This is the supply current when the output of the gate is at logic 1.
• Low-level output current, ICC (1).This is the supply current when the output of the gate is at logic 0.

#### 7. Noise Immunity

Specifically, it refers to circuits ability to withstand the noise without causing a change in the output. a quantitative measure of it is called noise margin.

However, if the noise in the circuit is high enough that it can push a logic 0 or may drop a logic 1 down into the illegal region. Meanwhile, the magnitude of voltage necessary to reach this voltage level is the Noise margin.

while Noise margin of high logic is;

NNH = VOH(min) – VIH(min)

whereas, the noise margin for low level is;

NNL = VIL(max) – VOL(max)

#### 8. Temperature

Chiefly the temperature range in which IC functions properly must be in between the ranges;

0 to 70. C _________(industrial purpose)

-55 to 125. C_______(Military purpose)

#### 9. Power Supply

Above all selecting the proper power supply for the gate is most important.

## Current Sourcing

When the output of the gate is high it supplies current to the load transistor, However, it also acts as a resistance to the ground.

## Current Sinking

The input circuitry of gate 2 is represented as a resistance tied to +VCC i.e. the positive terminal of power supply. When the gate 1 output goes to 0 the current will flow back from the input circuit of gate 2 through the output resistance of gate 1 to the ground.

## TTL Logic Family

Generally, the transistor logic is the most successful bipolar logic.

TTL family uses transistors for various logic functions and also for strong drive capability. The NAND gate is the most common TTL logic circuit. it specifically uses multiple emitter transistors. the number of inputs to the gate is equal to the emitter legs.

## TTL NAND Gate

Now let’s start by understanding that how TTL NAND gate works;

Case 1 when at least one input is low;

If any one of the inputs is low then, the emitter-base junction of T1 is in forward bias. whereas, the base-collector junction is a reverse bias which in turn switches off the transistor T2 and T4. and hence, as a result, the third transistor which is in contact with the source gets ON and as a result, the transistors gets a high output.

case 2, When both the inputs are high;

when both the input is high then, the emitter-base junction of transistor T1 is reverse bias whereas the collector base is a forward bias which in turn switches on the transistor T2 and T4 and switch off’s the transistor T3. Now as T3 is off the final output of the gate is low

## Active Pull-Up

It is possible in the TTL gate to hasten up the charging of output capacitance without increasing power usage with the means of an output arrangement known as active pull-up or totem pole output.

Wired AND connection must not be used for the totem pole output because of the spike problem(i.e. create noise in the signal and also increase the power consumption more so when the gate operates in high frequency ). TTL open collectors are available which can be used for wired ANDING.

## Open Collector Output

The circuit with an open collector is the same as that of the TTL NAND gate except for the collector-resistor RC3 of T3. The collector terminal C3 is present outside the IC and the passive pull up is given externally.

## CMOS Logic Family

A complementary MOSFET is obtained by connecting the NMOS and PMOS in series, with drain tied together. however in this case the output is also taken from the common drain terminal and input is given to the common gate terminal.

## CMOS NAND Gate

In the NAND gate, the NMOS driver is connected in series and PMOS in parallel.

Case 1 for instance when both the inputs are low;

If both the inputs are low, then both the PMOS will be ON and both the NMOS will be OFF. This will provide two paths through which the output can get a connection to the VDD(Source). However, there will be no path to the ground as both the NMOS are OFF. and hence as a result the final output will be HIGH.

Case 2 for instance A = Low and B = High;

PMOS 2 and NMOS 1 will be OFF because the potential at A is 0(low) on the other hand PMOS 1 and NMOS 2 will be ON. as the PMOS are in parallel there will be a route to VDD through PMOS 1 and no path to the ground as both the NMOS are in series. as a final result, the output line will be at a high level.

Case 3 for instance A = High and B = Low;

As the input B is at low voltage PMOS 1 and NMOS 2 will be OFF . as the PMOS is in parallel there will be a path to VDD through the PMOS 2 whereas no path to the ground because of their serial connection.

Case 4 for instance A = High and B= High

Id both the inputs are high then the PMOS 1 and PMOS 2 will be OFF and hence there will be no net voltage available at the gate.

## Conclusion

Consequently here we are to the last part of the blog. I hope that you liked it and are satisfied with the content given above. If you did then please do share it with others and also feel free to comment down below if there’s any doubt regarding the topic. Besides, I would be really happy to know which topic you would like to read next on.

Have a nice day:)

Regards.