Best of Programmable Logic Devices

Hello everyone, I hope that you all are doing good in your lives. In today’s blog, we are going to discuss various programmable logic devices. Certainly combinational and sequential digital circuits have been discussed before in the last few blogs. Various ICs for performing digital operations and other functions. For example multiplexer, demultiplexer, comparators, etc also have been discussed before. If you haven’t checked it before then please do go through the links below.

However the ICs mention above refers as fixed-function ICs, i.e each one of them performs a specific task. These devices are designed by the manufacturers in a large quantity to meet the needs of a wide variety of applications and are readily available. However, these methods have few disadvantages like, large board space requirements, lack of security, etc. To overcome the disadvantage of this method application-specific integrated circuits (ASICs) have been developed. These are designed by the user to meet the specific requirements of a circuit specified by the user. Usually, the design is too complex. However these methods have some disadvantages like development cost, the testing method may increase cost and effort. Thus another approach that has the advantages of both the above methods is the use of programmable logic devices.

Programmable Logic Devices

A programmable logic device is an IC that is user changeable and capable of implementing the logic functions. It is a VLSI chip that contains a regular structure and allows the designer to make changes according to the specific requirements. Thus the advantages of PLDs are;

  1. Short design cycle.
  2. Low development cost.
  3. Design security
  4. Reduce power requirement
  5. Lastly compact circuit

The PLDs allow users more flexibility to experiment with design because they can be reprogrammable in seconds. PLDs are also useful for prototyping ASIC design since they may require costly development.

Because of the various advantages of PLDs mention above, a large number of PLDs have been produced by IC development with a variety of options available. Further, we are going to discuss various architecture and options available for circuit designers.

Types of Programmable logic devices(PLD)

SPLDs (Simple programmable logic design)

ROM AS A Programmable Logic Devices


Read-only memory(ROMs) is basically a combinational circuit that can be used to carry out a logic function. A ROM of size M * N has M number of locations and N number of bits are allowed to store at each location.ROM block diagram

However, the address input is P, where 2P = M and the number of data input lines are N. We can simply also assume that the logic device has P inputs and N outputs.

For example the 16 bit ROM array has four inputs and one output, i.e M =16, N = 1 and P = 4.

In general a P variable, N output logic function can be implemented using a ROM of size 2p * N since all the possible 2P minterms are effectively generated.

If ROM is in use, then the user can specify the bit pattern to be stored according to the need of the logic function. But cannot change the values one stores. Whereas the user can himself program it in case of PROM, EPROM, E2PROM. Thus programmable ROMs can be used for logic design and thus it is referred as a PLD.


Programmable ROM allows the user to program the binary data electrically once. PROM is a programmable logic device in which the input connection matrix i.e. the AND array is fixed or hardwired and the output connection matrix i.e the OR array is programmable.

Thus the block diagram of PROM is ;block diagram of PROM as a programmable logic devices

Example Problem:-

Q.1 Implement the following Boolean equation using PROM

F1(A,B) = Σm(1,2)

F2 (A,B) = Σm(0,1,3)

These two functions are in the form of SOP and are having two variables each ( A and B ) thus, in this problem we need a 2: 4 decoder

Implementation of PROM

Here 2: 4 decoder forms 4 minterms. All of these 4 minterms can be connected to the two programmable OR gates However, only those which are required for the SOP form are programs.

  1. Easy to design.
  2. Design can be changed.
  3. Cost decreases.
  4. Lastly Usually faster than MSI/SSI circuits.
  1. Non utilization of the circuits.
  2. Increase power need.
  3. Increase in size.
  4. Lastly increasing number of input variables make it impractical to use.

Programmable array logic

A PLD usually consists of a programmable array of logic gates and interconnections with array input and output connected to the device pin through fixed logic elements, such as inverting/ non-inverting buffer. The logic gates may be a pair of two levels AND – OR, NAND – NAND, or NOR – NOR. In some cases, AND – OR – EX-OR configuration can also be used.

Basically, there are two varieties of Programmable logic devices, Programmable logic array (PLA) and Programmable array logic (PAL). However, both of these methods are suitable for the implementation of logic functions in form of SOP.

A PAL consists of both, AND – OR circuits on a single chip. The number of AND and OR gates and their inputs are fixed for a particular PAL chip. Certainly, the AND gate present here gives the product term and the OR gate logically sums these product terms and thereby forms an SOP equation.

It has M inputs, P product terms, and N outputs with P < 2M, and can be used to implement a logic function of M variables with N outputs. Since all of the possible 2M minterms are not available, Thus logic minimization is require.

As visible below one can see that a PAL consists of a programmable input matrix and fixed output matrix i.e. programmable AND array and fixed OR array. Meanwhile, in this method, we are allowed to generate only the required minterms instead of generating all. The output obtains by PAL are in SOP form.

However, the block diagram of PAL is;block diagram of PAL as programmable logic devices

Example Problem

Q.1 Implement the following Boolean equations using PAL;

P = XZ’ + X’Y’Z + YZ’

Q = X’Y’ + XY

R = YZ’

S = Z + X’Y

However, from we can see that in all of the four equations above we can we have 3 terms in all which are common. Thus we can conclude that we have 3 inputs and 4 outputs to represent the four equations. Therefore the subsequent PAL is;Implementation of PAL as a programmable logic device

  1. Highly secure
  2. Flexible
  3. Modification and design is quite easy
  4. Lastly decreases power consumption
  1. Expensive.
  2. Complex circuit.
  3. Lastly difficult in maintenance

Programmable logic array

A Programmable logic array (PLA) is completely the same as that of PAL the only difference is that in this method both the input and output matrix are programmable. In simple words, we can say that both AND and OR gates are programmable.

However, the block diagram of PLA is;block diagram of PLA as programmable logic devices

Example Problem

Q.1 Implement the following Boolean equation;

F1 ( A, B, C) = summation of m (3, 5,7)

F2 (A, B, C) = summation of m(4, 5, 7)

Thus the truth Table is;TRUTH TABLE

and thus the K-map;


Thus, F1 = AB’ + AC


Thus, F2 = AC + BC’

As we can see above in both the functions we are having two product terms each thus, we are going to need 4 logical AND gates and 2 logical OR gates to obtain this SOP form. Therefore subsequent PLA is;Implementation of PLA as a programmable logic device

  1. Easy implementation.
  2. Higher logic density.
  3. Less time consuming.
  4. Lastly error can be easily solved.
  1. Do not provide the user full decodibility as in available PROM.
  2. Lack of portability
  3. Large size
  4. Lastly less economical
  1. Control over data path
  2. Counters
  3. decoders
  4. Lastly as bus interference

Complex programmable logic devices

The SPLDs such as PALs, PROMs, PLAs, and GALs have limitations in the number of input, product terms, and outputs. Therefore these can only support circuits that require a total of 32 inputs and outputs.

Whereas for implementation of circuits with more components we use multiple SPLD chips on a single board or an advanced version CPLDs

A CPLD is nothing but a collection of SPLDs on a single chip and programmable interconnection structure.


However here we are at the end of the blog. I hope that all your doubts are been clear and you are satisfied with the content above. So if do like the blog then please make sure to share it with others and also mention the part which you like the most. Besides if are having any doubts regarding the topic then feel free to ask down below. And don’t forget to mention the topic which you would like to read next on.

Have a nice day 🙂


Read More

  1. Preface for 3-Phase Induction Motors
  2. Synopsis of Frequency Response & Filter Circuits
  3. Top Analysis of DC Circuits | Electrical Network | Part-2
  4. Top Analysis of DC Circuit | Electrical Network | Part-1
  5. 4 Major Types Of Flip Flop Circuits
  6. Differential Amplifier Vs Op-amp | Parameters
  7. Searching Algorithm in C | Linear VS Binary search

1 Comment

  • Ayushi April 26, 2021 at 11:25 am Reply


Leave a Comment