4 Major Types Of Flip Flop Circuits
Hello Everyone hope you all are doing good in your lives. So far we have bent our studies only towards the combinational digital circuits. Though it is very important, it consists of only a part of digital electronics. The other major aspect of a digital system is the analysis and design of sequential circuits. So in today’s blog, we are going to understand what sequential circuits are? types of flip flop circuits available? There design and analysis?
However, if you all haven’t been through combinational circuits they do refer to the blog mention below;
Introduction to types of flip flop circuits
The Flip flop is a basic component of a sequential logic system. Using flip flops and combinational logic circuits we can design a sequential logic. However, the most common use circuit is a register and comparators.
Moreover, these circuits are of two main types, known as asynchronous and synchronous sequential circuits depending on the timing of their signal.
A circuit that does not depend on the clock signal for the completion of the task but on the other hand uses various signals for indication purposes referrer to be as an asynchronous sequential circuit.
So sequential circuit whose behavior can be defined from the knowledge of its signal at discrete instant of time is referrer to be a synchronous sequential circuit.
A 1-bit Memory Cell
The basic digital memory circuit is understood as Flip flop. However, it has two stable states 0 and 1 . It can be obtained by using NAND or NOR gates. We shall be systematically developing a Flip flop circuit starting with the basic circuit shown in the diagram below. However, it consists of two inverters G1 and G2. The output G1 is attached to the input of G2 and the output of G2 is attached to the input of G1.
Let us consider the output of G to be Q=1, which is also the input of G2. Therefore, the output of G2 will be Q’=0, which makes A1=0 and consequently Q=1 which confirms our assumptions. In a similar manner, we can show that Q=0, then Q’=1 and this is also consistent with the circuit connections.
To sum up we can say that;
- Firstly the output Q and Q’ are complementary to each other in all cases.
- The circuit has two stable states i.e. 0 and 1
- If the circuit is in 1 state it continuous to be in that state and similarly if it is in 0 state it remains in this state. this property of circuit is to be refer as memory.
Since the information is lock or latched in this circuit they are also referring to be a latch.
Types Of Flip Flop Circuits
S-R Flip-Flop Circuit
It is furthermore required to set or reset the memory cell in sync with a train of pulses going by the name of a clock. So such a circuit is given below and is known as clock set-reset Flip flop.
Working
However in this circuit, if a clock pulse is present the circuit works as, If S=R=0, the circuit works exactly the same as that of a 1-bit memory cell. If S=1 and R=0, the output of G3 will be 0 and the output of the G4 will be 1. Since the output of G1 is zero, its output will certainly be one. Consequently, both the input ofG2 will be 1 giving an output Q’=0. Hence for this input state, Q=1 and Q’=0. Similarly if S=0 and R=1 then the output will be Q=0 and Q’=1. So if S=R=0 the output remains unaltered.
On the other hand, when the clock pulse is not preset, the gates G3 and G4 are reserved i.e. their output is one irrespective of the value of S or R.
Truth Table
| S | R | Output |
| 0 | 0 | Qn |
| 1 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 1 | ? |
J-K Flip flop circuit
The uncertainty within the state of an S-R Flip flop when Sn=Rn=1 is often eliminated by converting it into a J-K Flip flop. However the data inputs are J and K which are ANDed with Q’ and Q, respectively, to obtain S and R input i.e.
S = J*Q’
R = K*Q
A J-K Flip flop thus obtain is explained below,
Truth Table
| J | K | Output |
| 0 | 0 | Qn |
| 1 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 1 | Qn’ |
However, it is not necessary to use the AND gate in the figure below. Since the same function can be performed by adding an extra input terminal to each NAND gate to G3 and G4 with modification given in fig next to it.
Race around Condition for types of flip flop circuits
Moreover, the difficulty of both inputs 1 is not allowed in an S-R Flip flop is eliminated in the J-K Flip flop by using feedback connection from output to the input of the gates G3 and G4. \
Assume that the input does not change during the clock pulse, which is not true because of the feedback connections. Consider, for example, that the input J=K=1 and Q=0 as shown in the figure below is applied at the clock input. However, after a time interval ▲t equal to the propagation delay through two NAND gates in series, the output will change to Q=1. Moreover, now we have J=K=1 and Q=1 and after another time interval ▲t, the output will change back to Q=0. Hence we conclude that for the period tp of the clock pulse, the output can oscillate back and forth between zero and one. As a result of the clock pulse, the value of Q is unpredictable. Thus it is refere to be as a race-around condition.
The race around condition can be avoided if tp < ▲t < T. However it’s going to be tough to satisfy this inequality because of terribly small propagation delay in ICs. Besides a more practical method to overcome this is to use the J-K Master flip flop.
Master J-K Flip Flop Circuit
Moreover, the master J-K Flip flop is a cascade of two S-R Flip flops, with feedback from the outputs of the second to the input of the first as shown below. The positive clock pulse is applied to the first flip flop and the clock pulse are inverted before Appling to the second flip flop.
Whenever CK=1 the first flip flop is enabling and the output Qm and Qm’ respond to the input J and K. At this time, the second flip flop is prohibited because its clock is low when CK goes low, the first flip flop prohibited and the second flip flop is enable because now its clock is high. Therefore the output Q and Q’ follow the output Qm and Qm’ respectively. Since the second flip flop simply follows the first one, thus it is refer to be as a master. Hence configuration is called a master-slave flip flop.
D Types Flip Flop circuit
whenever we use only two middle rows of the truth table of the S-R or J-K Flip flop, we obtain a D-Type Flip flop. However, it has only one input referred to as D input or data input.
Truth Table
| Input | Output |
| 0 | 0 |
| 1 | 1 |
Moreover, this is equivalent to say that the input data appears at the output at the end of the clock pulse. Thus, the transfer of data from output is delayed, and hence the name delay flip flop. The D-type flip flop is either use as a delay device or as a latch to store one bit of binary information.
T Type Flip Flop Circuit
Whenever in a J-K Flip flop, If J=K, the resulting flip flop is refer as a T-Type flip flop and is shown below. It has only one input, refer as T-input.
Truth Table
| Input | Output |
| 0 | Qn |
| 1 | Qn’ |
Thus from the truth table, it is clear that T=1 acts as a toggle for every clock pulse, the output Q changes. However, an S-R Flip flop cannot be converted into a T flip flop as S=R=1 is not allowed. However, the circuit below acts as a toggle i.e. the output Q complements with every clock pulse.
Conclusion
Lastly here we are to the last part of our blog. I hope that you liked it is and have got all your doubts clear. However, if you all are having any doubts then feel free to ask down below in the comments at would really like to know which part you liked the most. Besides all thanks for being a part and please acknowledge the topic that you would like to read next on
Have a nice day 🙂
Regards.
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